First generation emulation systems were formed using general purpose reconfigurable integrated circuits (ICs) without integrating debugging facilities, such as general purpose field programmable gate arrays (FPGAs), and reconfigurable interconnects, such as crossbars. To emulate a circuit design on one of such emulation systems, the circuit design would be “realized” by compiling a formal description of the circuit design (expressed, e.g., in the hardware description language Verilog), partitioning the circuit design into subsets (also referred to as netlists), mapping the various subsets (netlists) to the logic elements (LEs) of the FPGAs of various logic boards of the emulations system, and then configuring the reconfigurable interconnects to interconnect the LEs. The partitioning and mapping operations would be typically performed on workstations that are part of or complementary to the emulation systems. The resultant configuration information, i.e., the information to configure the logic elements and/or interconnects, would be downloaded onto logic boards hosting the reconfigurable logic ICs and reconfigurable interconnect ICs, and then onto the reconfigurable logic ICs and reconfigurable interconnect ICs themselves.
During emulation, test stimuli are either generated on the workstation or on a service board of the emulation system under the control of the workstation, and then transferred to the various logic boards for input into the reconfigurable logic ICs for application to the various netlists of the circuit design being emulated. To emulate the operation of the circuit design, emulation signals often must be transferred from one reconfigurable logic IC to another. At appropriate points in time, state data of various circuit elements as well as various signals of interest of the circuit design being emulated, would be read out of the appropriate reconfigurable logic ICs and then transferred off the logic boards for analysis on the companion workstation.
With advances in integrated circuit and emulation technology, some late model emulation systems would employ FPGAs specifically designed for emulation purposes. These special FPGAs typically would include a substantial number of on-chip reconfigurable logic elements, interconnects, memory, and debugging resources. As the advances continue, more of these resources are packed into each FPGA, enabling more circuit elements to be “realizable” and “emulate-able” on each FPGA. This has resulted in, the pin to logic element ratio, i.e., the number of pins available to transfer signals of the circuit under emulation off one emulation IC to another emulation IC, to steadily decline.
Some emulation systems employ what is referred to as a time domain multiplexing approach, allocating multiple signals to share a physical pin/interconnect over time. For example, assume that three emulation signals (A, B and C) need to be routed from one reconfigurable logic IC to another reconfigurable logic IC. The three emulation signals may be assigned or allocated to share the same physical pin or wire. During an emulation cycle, the physical pin/wire is used to transfer the three signals, in turn, in three sub-cycle periods of the emulation clock in a predetermined order, e.g. A, B, C, or B, C, A. These systems suffer from a number of known disadvantages. For example, straight time multiplexing or time division (of the emulation clock) cannot be used for circuit designs having asynchronous signals.
Thus, an improved approach to transferring emulation signals between reconfigurable logic or interconnect ICs in an emulation system is desired.